MIT researchers have developed a new type of 3D transistor that could be more energy-efficient and powerful than current silicon-based transistors.

The novel 3D transistors have been designed using ultrathin semiconductor materials.

“This is a technology with the potential to replace silicon, so you could use it with all the functions that silicon currently has, but with much better energy efficiency,” said Yanjie Shao, an MIT postdoc and lead author.

The transistors harness quantum mechanics to achieve high performance at low voltage within a nanoscale area.

Their minuscule size paves the way for a new era of ultra-dense, high-performance, and energy-efficient electronics.

Overcoming limitations

Silicon transistors function as electronic switches. A simple voltage application triggers a dramatic state change in the transistor, from off to on. This on/off state represents binary digits, enabling computation.

The efficiency of a transistor is linked to its switching slope. A steeper slope directly correlates to lower energy consumption. This means that the transistor can be switched on and off quickly, requiring less time and, consequently, less energy.

However, a fundamental limitation known as Boltzmann tyranny imposes a minimum voltage requirement for transistor operation at room temperature.

This limit is generally found in silicon transistors. 

To overcome it, these new transistors use ultrathin semiconductor materials and quantum mechanics to achieve high performance at low voltage.

MIT researchers turned to gallium antimonide and indium arsenide semiconductor materials. 

Furthermore, they incorporated quantum tunneling principles into their device architecture. In this phenomenon, electrons can penetrate potential barriers.

“Now, you can turn the device on and off very easily,” Shao added.

The transistor’s unique geometry

However, tunneling transistors often suffer from low current output. This limitation hinders their performance in demanding applications that require high currents for efficient operation.

To address this, the engineers worked on the 3D geometry of the transistors. For this, they fabricated nanowire heterostructures with a diameter of only 6 nanometers.